CPU Formal Verification Intern Review

As a formal verification engineer, my role is to investigate and bring up new formal verification flows for different CPU units. This involves scripting, writing SystemVerilog, reading RTL code and documentation, and communicating with my team, manager and designers about flow improvements. The role also involves debugging waveforms on counterexamples found by the formal flow.

I was given the responsibility of bringing up an entire verification flow on my internship. Although this was a large and daunting task at the beginning, my supervisor and team were always on hand to help, and my work was not on the "critical path", so to speak, so I got a great experience of doing real work but on a unit which wasn't required to be completed for the project milestone.

I learnt about formal verification.
I learnt how to write YAML, Tcl and how to use the formal verification tools (JasperGold).
I developed my skills in SystemVerilog, Python, debugging, and computer architecture.
I also improved my confidence and communication during the internship.

At the beginning of my internship, I had one-to-one catch-up calls with my supervisor every day to help ensure I didn't get stuck and was on track. As the internship progressed, I became more independent, but still had at least weekly catch-ups with my supervisor, biweekly catch-ups with my line manager, and unit-specific and whole team meetings every week. However the formal team was always very happy to help and answer questions whenever.

Very pleasant company culture, everyone is very helpful and happy to support you. General atmosphere is that the employees at Arm are very happy and enjoy their work, and the work is rewarding and fulfilling

I thoroughly enjoyed my internship, I was doing meaningful enjoyable work which was actually used in the main project. I also developed so many skills during my internship. Cannot recommend enough.

Yes